The present invention relates to a semiconductor memory device, and more particularly, to a voltage boosting circuit (the term referred to herein as a "voltage boosting circuit" has the same meaning in this field as a boosting circuit, a boosting voltage generating circuit, a bootstrap circuit, etc.) for boosting a supply voltage supplied from a system to a desired boosting voltage level.
In a semiconductor memory device such as a dynamic RAM (random access memory) etc., the transmission of data can cause a shift of an effective voltage potential of the memory. In a dynamic RAM consisting of CMOS transistors, there occurs a voltage drop by the threshold voltage of the MOS transistor while the potential is transmitted through the channel region of the MOS transistor. This inevitable voltage drop becomes an obstacle to the accurate reading or writing of data as well as potentially causing the loss of data. To solve such a problem, a voltage boosting circuit for raising a voltage level has come to be used. As techniques for such a voltage boosting circuit, there are Korean patent No. 91-19740, filed Nov. 7, 1991, assigned to Samsung Electronics Co., Ltd. of Kyungki-do, Rep. of Korea, entitled "A VOLTAGE BOOSTING CIRCUIT"; a paper entitled "A 35 ns 64 Mb DRAM Using On-Chip Boosted Power Supply", 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 64-65; U.S. Pat. No. 4,704,706 granted to Japan Fujitsu Co.; and the like.
FIG. 1 schematically shows a characteristic portion of a voltage boosting circuit which is generally well known in the art and described in the aforementioned techniques. An input node 2 receives an oscillating signal .phi.OSC generated from an oscillator (not shown). A pumping capacitor 4 has one terminal of the electrode coupled to the input node 2 and the other terminal of the electrode coupled to a pumping node 8. A pumping capacitor 6 has one terminal of the electrode coupled to the input node 2 and the other terminal of the electrode coupled to a pumping node 10. A transmission transistor 12 with the gate and drain connected to the pumping node 8 and 10 respectively generates a boosting voltage VPP. Although not shown in FIG. 1, there is further provided a precharge circuit for precharging the pumping nodes 8 and 10 to a supply voltage VCC level. The construction of FIG. 1 is known in the art as a charge pump circuit. The oscillator operates when the boosting voltage VPP is lowered to a level lower than a normal level by an internal circuit during power-up of a chip and during the active cycle. If the oscillating signal .phi.OSC is supplied to the input node 2, the pumping capacitors 4 and 6 boost the pumping nodes 8 and 10 to about twice the supply voltage VCC. A voltage charged to the pumping node 10 is generated through the channel of the transmission transistor 12 as the boosting voltage VPP. The circuit of FIG. 1 is driven by the oscillator using as source voltage the supply voltage VCC, so that the boosting voltage VPP level of 2 VCC-VT (where VT is the threshold voltage of the transmission transistor 12) can be obtained. The pumping nodes 8 and 10 are initially precharged to the supply voltage VCC level.
The voltage boosting circuit of FIG. 1 is formed by a typical CMOS manufacturing process. The circuit of FIG. 1 has the problem of pumping efficiency in that the transmission transistor 12 is an NMOS transistor formed by the CMOS manufacturing process. As is well known to those skilled in the art, the MOS transistor has device characteristics that a body effect increases with the increase in a voltage level across its source and drain. It is apparent that the body effect further increases since the size of each device is shortened and space thereof becomes narrower with increasing integration of a semiconductor memory device. The boosting voltage circuit of FIG. 1 has a fundamental problem that the pumping efficiency is lowered by the device characteristics of the MOS transistor, i.e. of the transmission transistor, rather than by circuit design.